Search - stopwatch vhdl

[Other resource] eclock

Description: MAXPULS II 下VHDL实现多功能电子钟的源代码，包括时钟，秒表，日历等多种功能-MAXPULS II under VHDL multifunctional electronic clock source code, including the clock, stopwatch, multiple functions such as calendar
Platform: | Size: 3075 | Author: 余远恒 | Hits:

[Other resource] EDA_miaobiao

Description: 《数字电路EDA入门－VHDL程序实例》---数字秒表程序例子-"digital circuit EDA portal-VHDL program examples" -- digital stopwatch procedures example
Platform: | Size: 1381 | Author: 张文 | Hits:

[Other resource] byvhdstopwatchl

Description: 1.高精度数字秒表（0.01秒的vhdl语言实现） 2.具有定时，暂停，按键随机存储，翻页回放功能； 3.对30M时钟分频产生显示扫描时钟 4.精度高达0.01s,并且可以通过改变主频来更改分频比和记数间隔，可控性高。 5.模块化设计，其中的许多函数可以成为vhdl语言的通用经典例子（包含分频电路设计，动态扫描时钟设计，译码电路设计，存储器设计，存储回放显示设计）-1. High-precision digital stopwatch (0.01 seconds vhdl language) 2. With a timer, suspended Random memory keys, flip playback function; 3. right 30M clock frequency scan have revealed four clock. Precision high 0.01s and and can be changed to alter the frequency than the frequency interval and Hutchison, controlled high. 5. Modular design, Many of these functions can become the common language vhdl classic examples (including sub-frequency circuit design, Dynamic scanning clock design, decoding circuit design, memory design, storage intervals showed Design)
Platform: | Size: 1995 | Author: 方周 | Hits:

[File Operate] VHDLEXAMPLEppt

Description: 介绍8位加法器、分频电路、数字秒表的PPT，带源码，解释详细，一步一步学习，是学习VHDL的好-introduced eight Adder, the frequency divider circuit, digital stopwatch, the PPT, with the source code, explained in detail, step by step, learning, VHDL is a good learning Eastern
Platform: | Size: 527607 | Author: 刘一 | Hits:

[Software Engineering] DigitalssStopwatch

Description: 本秒表计时器用于体育竞赛及各种要求有较精确时的各领域。此计时器是用一块专用的芯片，用VHDL语言描述的。它除开关、时钟和显示功能以外，它还包括1/100s计时器所有的控制和定时功能，其体积小，携带方便。-the stopwatch timer for the various sports competitions and requires more accurate at the various fields. This timer is a dedicated chip, using the VHDL description. In addition to its switch, the clock and display functions, but also include 1 / 100 seconds timer control and all the regular functions, its small size and easy to carry.
Platform: | Size: 6951 | Author: 段苛苛 | Hits:

[VHDL-FPGA-Verilog] shuzimiaobiao

Description: 数字秒表的VHDL设计,能精确到百分秒,在6位数码管上显示,分别有秒,分,小时,通过目标芯片EPF10KLC84-4验证-VHDL design of digital stopwatch, accurate to the percentage of seconds in the six digital tube display, respectively, have seconds, minutes, hours, through the target chips EPF10KLC84-4 verification
Platform: | Size: 460800 | Author: ellala | Hits:

[VHDL-FPGA-Verilog] clock

Description: 用vhdl实现的多功能时钟,有整点响铃,秒表等多种功能-Use VHDL to achieve multi-functional clock, there is the whole point of the bell to ring, a variety of functions such as stopwatch
Platform: | Size: 2048 | Author: liaocongliang | Hits:

[VHDL-FPGA-Verilog] shiyan3_24

Description: 多功能秒表的设计，VHDL实现，对学习数字逻辑的同学有帮助。-Multi-function stopwatch design, VHDL realize, the students study digital logic has to help.
Platform: | Size: 441344 | Author: ZhengHuazhen | Hits:

[VHDL-FPGA-Verilog] second

Description: 关于VHDL写的秒表程序，有模块，顶层文件，仅供参考-On the stopwatch to write VHDL procedures modules, top-level documents, for reference only
Platform: | Size: 478208 | Author: 娃娃 | Hits:

[source in ebook] stopwach

Description: vhdl stopwatch -quartus2 -vhdl stopwatch-quartus2
Platform: | Size: 705536 | Author: je | Hits:

[VHDL-FPGA-Verilog] szmiaobiao

Description: 　应用VHDL语言设计数字系统，很多设计工作可以在计算机上完成，从而缩短了系统的开发时间，提高了工作效率。本文介绍一种以FPGA为核心，以VHDL为开发工具的数字秒表，并给出源程序和仿真结果。 -Application of VHDL language design digital systems, a lot of design work can be completed on the computer, thereby reducing system development time and improve efficiency. This article describes an FPGA as the core, a tool for the development of VHDL digital stopwatch, and the source code and simulation results are given.
Platform: | Size: 627712 | Author: yyyyyy | Hits:

[VHDL-FPGA-Verilog] Digital-stopwatch

Description: 1、了解数字秒表的工作原理。 2、进一步熟悉用VHDL语言编写驱动七段码管显示的代码。 3、掌握VHDL编写中的一些小技巧。 -1, to understand the working principle of digital stopwatch. 2, more familiar with the use of VHDL language driver seven segment display code. 3, master VHDL prepared some of the tips.
Platform: | Size: 1602560 | Author: | Hits:

[VHDL-FPGA-Verilog] stopwatch-based-on-VHDL

Description: 基于VHDL的电子秒表的设计，使用VHDL语言描述一个秒表电路，利用QuantusII软件进行源程序设计，编译，仿真，最后形成下载文件下载至装有FPGA芯片的实验箱，进行硬件测试，要求实现秒表功能。-Design of electronic stopwatch based on VHDL
Platform: | Size: 1024 | Author: 煌釨 | Hits:

[VHDL-FPGA-Verilog] Example23

Description: 设计一款多功能数字秒表的VHDL小程序，产生100Hz时钟的分频计数器-Design a multi-function digital stopwatch VHDL applet, generate 100Hz clock divider counter
Platform: | Size: 284672 | Author: 卢进 | Hits:

[Other] stopwatch

Description: VHDL秒表设计，硬件环境为NEXYS4开发板，有暂停功能，7段数码管显示。-VHDL stopwatch design, the hardware environment for the NEXYS4 development board, a pause function, 7 digital tube display.
Platform: | Size: 733184 | Author: jim | Hits:

[VHDL-FPGA-Verilog] stopWatch

Description: 基于VHDL语言数字秒表的实现！使用模块化的设计，包含详细设计说明文档。可在DE2-115开发板上进行验证！-digital stop watch based on VHDL language
Platform: | Size: 493568 | Author: 顾庆水 | Hits:

[Other] stopwatch

Description: stop watch vhdl code
Platform: | Size: 159744 | Author: ali elgammal | Hits:

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[Other resource] eclock

[Other resource] EDA_miaobiao

[Other resource] byvhdstopwatchl

[File Operate] VHDLEXAMPLEppt

[Software Engineering] DigitalssStopwatch

[VHDL-FPGA-Verilog] shuzimiaobiao

[VHDL-FPGA-Verilog] clock

[VHDL-FPGA-Verilog] shiyan3_24

[VHDL-FPGA-Verilog] second

[source in ebook] stopwach

[VHDL-FPGA-Verilog] szmiaobiao

[VHDL-FPGA-Verilog] Digital-stopwatch

[VHDL-FPGA-Verilog] stopwatch-based-on-VHDL

[VHDL-FPGA-Verilog] Example23

[Other] stopwatch

[VHDL-FPGA-Verilog] stopWatch

[Other] stopwatch

[VHDL-FPGA-Verilog] szmb

[VHDL-FPGA-Verilog] 秒表

[VHDL-FPGA-Verilog] 课程设计-数字钟

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